Processor to execute shift right merge instructions

摘要

Method, apparatus, and program means for performing bitstream buffer manipulation with a SIMD merge instruction. The method of one embodiment comprises determining whether any unprocessed data bits for a partial variable length symbol exist in a first data block is made. A shift merge operation is performed to merge the unprocessed data bits from the first data block with a second data block. A merged data block is formed. A merged variable length symbol comprised of the unprocessed data bits and a plurality of data bits from the second data block is extracted from the merged data block.

主权项

1. An apparatus adapted for use in a cellular phone comprising: a plurality of registers to store 128-bit operands;
a decoder to decode a single instruction multiple data (SIMD) instruction having a 32-bit instruction format, the SIMD instruction to indicate a first 128-bit operand having a first set of sixteen bytes and a second 128-bit operand having a second set of sixteen bytes, the SIMD instruction to have a 4-bit immediate to specify a number (n) of bytes; a unit coupled with the decoder and the plurality of registers, the unit in response to the SIMD instruction to store a 128-bit result in a destination to be indicated by the instruction, wherein the result is to include
the number (n) least significant bytes, of the second operand in the number (n) most significant bytes of the result,concatenated with sixteen minus the number (n) most significant bytes of the first operand in sixteen minus the number (n) least significant bytes of the result, andwherein the SIMD instruction is of a type that is capable of processing elements of a plurality of sizes including at least 8-bit byte elements, 16-bit elements, and 32-bit elements,wherein the sixteen bytes of the first 128-bit operand include one of the 16-bit elements and the 32-bit elements,wherein the apparatus implements a combination of instruction sets; a flash memory interface to interface with a flash memory of the cellular phone; a synchronous dynamic random access memory (SDRAM) interface to interface with an SDRAM of the cellular phone; a universal serial bus (USB) interface to interface with a USB of the cellular phone; and a Bluetooth wireless universal asynchronous receiver/transmitter (UART) interface to interface with a Bluetooth UART of the cellular phone.