Dynamic random access memory for a semiconductor storage device-based system

摘要

Embodiments of the present invention provide an approach for dynamic random access memory (DRAM)/SSD-based memory to improve memory usage. Specifically, embodiments of the present invention provide a field programmable gate array (FPGA) (SSD controller) that comprises a PCI-express interface for receiving and converting serial data to 64 bit data; a data/bit converter coupled to the interface for converting the 64 bit data to 128 bit data; and a memory controller coupled to the data converter for receiving and storing the 128 bit data in a set of DRAM units coupled to the memory controller. In general, the data converter comprises an input address buffer for receiving and buffering address information; an address matching component coupled to the input address buffer for analyzing the address information and determining a matching address based on the address information; an output address buffer coupled to the address matching component for buffering and outputting the matching address; an input data buffer for receiving and buffering 64 bit data; a data matching component coupled to the input data buffer for matching the 64 bit data with a corresponding address; and an output data buffer coupled to the data matching component for buffering and outputting the 128 bit data based on output of the data matching component.

主权项

1. A controller for a dynamic random access memory (DRAM)-based semiconductor storage device (SSD) system, comprising:
an interface for receiving and converting serial data to 64 bit data; a data converter coupled to the interface for converting the 64 bit data to 128 bit data, wherein memory addresses for storage of the 64 bit data in a set of DRAM units are analyzed to determine a matching address; and a memory controller coupled to the data converter for receiving and storing the 128 bit data in the set of DRAM units coupled to the memory controller.