发明名称 |
Wafer-level molded structure for package assembly |
摘要 |
An integrated circuit structure includes a bottom die; a top die bonded to the bottom die with the top die having a size smaller than the bottom die; and a molding compound over the bottom die and the top die. The molding compound contacts edges of the top die. The edges of the bottom die are vertically aligned to respective edges of the molding compound. |
申请公布号 |
US8743561(B2) |
申请公布日期 |
2014.06.03 |
申请号 |
US20100813979 |
申请日期 |
2010.06.11 |
申请人 |
Taiwan Semiconductor Manufacturing Company, Ltd. |
发明人 |
Wang Tsung-Ding;Lee Bo-I;Lee Chien-Hsiun |
分类号 |
H05K1/00 |
主分类号 |
H05K1/00 |
代理机构 |
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代理人 |
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主权项 |
1. An integrated circuit structure comprising:
a bottom die; a top die bonded to the bottom die, wherein the top die has a size smaller than the bottom die; a molding material over and in between the bottom die and the top die, wherein the molding material extends to and contacts edges of the top die and extends along and contacts an entirety of a top surface of the top die, and wherein edges of the bottom die are vertically aligned with respective edges of the molding material; and a package substrate underlying and bonded to the bottom die using solder balls.
|
地址 |
Hsin-Chu TW |