Delay-locked loop having a loop bandwidth dependency on phase error

摘要

Circuits, methods, and apparatus that vary one or more attributes or parameters of a closed-loop clock circuit as a function of a characteristic of its phase error. One example provides a delay-locked loop having a loop bandwidth that can be varied as a function of its phase error. In this specific example, current phase error is determined. This determination may be made directly, either by measuring phase error, or indirectly, by determining if phase error is within one or more ranges of values. Once the phase error is determined, the loop bandwidth can be set. In one example, the loop bandwidth is set by adjusting the depth, type, or depth and type of the delay-locked loop's loop filter. In this way, large phase errors can be reduced quickly by increasing loop bandwidth, while small phase errors can be used to decrease loop bandwidth, thereby improving jitter performance.

主权项

1. A method of providing a clock signal, the method comprising:
determining a characteristic related to a phase error for the provided clock signal; setting an attribute of a closed-loop clock circuit based on the determined characteristic; receiving the clock signal with the closed-loop clock circuit; and providing a retimed clock signal with the closed-loop clock circuit, wherein the attribute comprises a filter depth.