| 摘要 |
A power on reset circuit is provided to improve stability of a system by not generating an additional reset signal even though an operation voltage of a power terminal is lower than a threshold voltage. A reset voltage output unit(300) includes a resistor, a capacitor, and a PMOS transistor(PM11). The PMOS transistor outputs an operation voltage of the power terminal by being conducted for a time constant of the resistor and the capacitor. The capacitor(C12) for generating a reset signal charges the reset voltage outputted from a reset voltage output unit. An inverter generates a reset signal by inverting a charging voltage of the capacitor. A current sink(310) delays the operation voltage of the power terminal. The current sink unit prevents an inverter from outputting the reset signal by discharging a charging voltage of the capacitor when the set delay time elapses. |
