Level shifter

摘要

The present invention provides a level shifter. In an embodiment, the level shifter includes first to sixth transistors. The first and second transistors have common control nodes coupled to a first bias voltage, receive a pair of input signals and respectively provide a first output node and a second output node. The fifth and sixth transistors have common control nodes coupled to a second bias voltage to form a current mirror. The third transistor is coupled between the first and the fifth transistors and has a control node coupled to the second output node. The fourth transistor is couple between the second and the sixth transistors and has a control node coupled to the first output node.

主权项

1. A level shifter, outputting a first output signal and a second output signal respectively from a first output node and a second output node according to a first input signal and a second input signal, wherein the first input signal and the second input signal operating between a first voltage and a common voltage, the first output signal and the second output signal operating between a second voltage and the common voltage, the first voltage being between the second voltage and the common voltage, and the level shifter comprising:
a first transistor, comprising a first primary-node, a first secondary-node and a first control node, the first primary-node receiving the first input signal, the first control node being keep at a first bias voltage, and the first secondary-node being coupled to the first output node, wherein the first bias voltage is provided by a first current mirror; a second transistor, comprising a second primary-node, a second secondary-node and a second control node, the second primary-node receiving the second input signal, the second control node being keep at the first bias voltage, and the second secondary-node being coupled to the second output node; a third transistor, comprising a third primary-node, a third secondary-node and a third control node, the third primary-node being coupled to the first output node, and the third control node being coupled to the second output node; a fourth transistor, comprising a fourth primary-node, a fourth secondary-node and a fourth control node, the fourth primary-node being coupled to the second output node, and the fourth control node being coupled to the first output node; a fifth transistor, comprising a fifth primary-node, a fifth secondary-node and a fifth control node, the fifth control node being coupled to a second bias voltage, the fifth secondary-node being coupled to the second voltage, and the fifth primary-node being coupled to the third secondary-node, wherein the second bias voltage is provided by a second current mirror; and a sixth transistor, comprising a sixth primary-node, a sixth secondary node and a sixth control node, the sixth control node being coupled to the second bias voltage, the sixth secondary-node being coupled to the second voltage, and the sixth primary-node being coupled to the fourth secondary-node; wherein the first transistor and the second transistor are matched, the fifth transistor and the sixth transistor are matched, when the first input signal equals the first voltage, the first output signal equals the second voltage, or when the first input signal equals the common voltage, the first output signal equals the common voltage, the first current mirror comprises a seventh transistor with a drain, a gate and a source respectively coupled to a first current source, kept at the first bias voltage and kept at the common voltage; wherein, the second current mirror comprises an eighth n-channel MOS transistor with a drain, a gate and a source respectively coupled to a second current source, the fifth control node and the second voltage, and a current of the first current source is greater than a current of the second current source.