Semiconductor device and manufacturing method thereof

摘要

In a semiconductor chip in which LDMOSFET elements for power amplifier circuits used for a power amplifier module are formed, a source bump electrode is disposed on an LDMOSFET formation region in which a plurality of source regions, a plurality of drain regions and a plurality of gate electrodes for the LDMOSFET elements are formed. The source bump electrode is formed on a source pad mainly made of aluminum via a source conductor layer which is thicker than the source pad and mainly made of copper. No resin film is interposed between the source bump electrode and the source conductor layer.

主权项

1. A power amplifier module, comprising:
a multilayer wiring board having a core layer, a first insulating layer formed on the core layer and a second insulating layer formed below the core layer; and a semiconductor chip including an LDMOSFET element for power amplification, the semiconductor chip being mounted on the multilayer wiring board, wherein the multilayer wiring board has a plurality of first vias formed in the core layer, a plurality of second vias formed in the first insulating layer, a plurality of third vias formed in the second insulating layer and a plurality of lands formed on an upper surface of the multilayer wiring board, the plurality of lands including a plurality of source lands, the semiconductor chip has a plurality of bump electrode pads including a source pad, a drain pad and a gate pad of the LDMOSFET element on a first main surface of the semiconductor chip, the semiconductor chip is mounted so that the first main surface faces the upper surface of the multilayer wiring board, the source pad having a plurality of source bump electrodes, each source bump electrode is electrically and mechanically connected to a respective one of the plurality of source lands, a plurality of second source vias out of the plurality of second vias are disposed below the plurality of source lands, each second source via being electrically connected to a respective one of the plurality of source lands, a plurality of first source vias out of the plurality of first vias are disposed below the plurality of second source vias, each first source via being electrically connected to a respective one of the plurality of second source vias, and a plurality of third source vias out of the plurality of third vias are disposed below the plurality of first source vias, each third source via being electrically connected to a respective one of the plurality of first source vias.