| 摘要 |
An interconnected array of reconfigurable logic cells which carry out at least one logic function, externally connected to peripheral connection network equipped with switch boxes and connected to programmable input/output blocks. The logic cells are distributed in a first dimension in rows i with i=1 to d and a second dimension in columns j with j=1 to w, with d≦2 and w=2 or d=2 and w≦2, each logic cell including a second input, a second input, a first output and a second output, the first input of each logic cell and the first output of each logic cell being connected to the connection network, the second input and the second output of each logic cell being connected to other different column and row logic cells except for the first and last rows or columns for d>2 or w>2 respectively. |
| 主权项 |
1. An interconnected array of reconfigurable logic cells carrying out at least one logic function (F), externally connected to peripheral connection network (5) equipped with switch boxes (6) and connected to programmable input/output blocks, characterized in that the logic cells [i, j] are distributed along a first dimension in rows i with i=1 to d and along a second dimension in columns j with j=1 to w, with d≧2 and w=2 or d=2 and w≧2, each logic cell including a first input (E1), a second input (E2), a first output (S1) and a second output (S2), the first input (S1) of each logic cell and the first output (S1) of each logic cell being connected to the connecting network (5), the second input (E1) and the second output (S2) of each logic cell being connected to other different column and row logic cells except for the first and last rows of columns for d>2 or w>2 respectively, through an intersection interconnecting topology between both columns of the array for w=2 and between both rows of the array for d=2 and successively oscillating along one direction and along one reverse direction, so that the logic depth of the logic functions (F) is comprised between 1 and 2×d or between 1 and 2×w;
wherein the connecting network (5) includes two sides (51) for connection with the rows (i) thus extending on either side of the first and second columns of the array on the one hand and two sides (52) for connection with the columns (j) thus extending on either side of the first and last rows (i) of the array; wherein for d>2, the first input (E1), and the first output (S1) of each logic cell belonging to a same column, except for the logic cells of the first row and of the last row, are connected to the side (51) for connection with the rows close to said column while for w>2, the first input (E1) and the first output (S1) of each logic cell belonging to a same row, except for the logic cells of the first and of the last column, are connected to the side (52) for connection with the columns, close to said row; and wherein the first input (E1) and the first output (S1) of each logic cell of the first and last rows for d>2 and of the first and last columns for w>2 are respectively connected to the neighboring side (51) for connection with the rows and to the neighboring side (52) for connection with the columns.
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