发明名称 Emulation system for verifying a network device
摘要 Various embodiments of the present invention are generally directed to a method and system for functionally verifying a network device design programmed into a hardware logic verification system. The method and system encapsulates and de-encapsulates test patterns generated by a tester application into and out of network packets, which are further encapsulated into and de-encapsulated from enclosing data packets for fast and efficient delivery to the network device. Such method and system decreases functional verification times for a network device DUT while requiring little to no modification of existing tester applications and functional verification hardware.
申请公布号 US8743735(B1) 申请公布日期 2014.06.03
申请号 US201213353122 申请日期 2012.01.18
申请人 Cadence Design Systems, Inc. 发明人 Bershteyn Mikhail;Seeley Stephen Frederick
分类号 H04L12/28 主分类号 H04L12/28
代理机构 代理人
主权项 1. A method of functionally verifying a network device design, comprising: a) programming the network device design into a hardware logic verification system comprised of a plurality of hardware emulation resources; b) establishing a network tunnel between a client endpoint and a server application of the hardware logic verification system, wherein the network tunnel feeds a plurality of first data packets to a socket of the server application of the hardware logic verification system; c) de-encapsulating a second data packet generated by a tester application from within a first data packet of the plurality of first data packets, wherein the second data packet comprises test patterns generated by the tester application and one or more second headers, and wherein the first data packet includes one or more first headers in addition to the second data packet; and d) receiving the test patterns at the programmed network device.
地址 San Jose CA US