发明名称 |
Computationally efficient modeling and simulation of large scale systems |
摘要 |
A system for simulating operation of a VLSI interconnect structure having capacitive and inductive coupling between nodes thereof, including a processor, and a memory, the processor configured to perform obtaining a matrix X and a matrix Y containing different combinations of passive circuit element values for the interconnect structure, the element values for each matrix including inductance L and inverse capacitance P, obtaining an adjacency matrix A associated with the interconnect structure, storing the matrices X, Y, and A in the memory, and performing numerical integration to solve first and second equations. |
申请公布号 |
US8745563(B2) |
申请公布日期 |
2014.06.03 |
申请号 |
US201213710145 |
申请日期 |
2012.12.10 |
申请人 |
Purdue Research Foundation |
发明人 |
Jain Jitesh;Cauley Stephen F;Li Hong;Koh Cheng-Kok;Balakrishnan Vankataramanan |
分类号 |
G06F17/50 |
主分类号 |
G06F17/50 |
代理机构 |
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代理人 |
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主权项 |
1. A system for simulating operation of a VLSI interconnect structure having capacitive and inductive coupling between nodes thereof, comprising:
a processor; and a memory, said processor configured to:
obtaining a matrix X and a matrix Y containing different combinations of passive circuit element values for said interconnect structure, said element values for each matrix including inductance L and inverse capacitance P,obtaining an adjacency matrix A associated with said interconnect structure,storing said matrices X, Y, and A in said memory, andperforming numerical integration to solve first and second equations each including as a factor product of inverse said matrix X (X−1) and at least one other matrix, said first equation including X−1Y, X−1A, and X−1P, and said second equation including X−1A and X−1P.
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地址 |
West Lafayette IN US |