Inter-processor communication apparatus and method

摘要

Inter-processor communication (IPC) apparatus and a method for providing communication between two processors having a shared memory, the IPC apparatus including an arbitrated bus coupling the processors to one another and to the memory, a buffer in the shared memory associated with each processor, and at least one pair of First In First Out hardware units (FIFOs) coupled to each processor, the FIFOs holding pointers to addresses in the buffer associated with that processor, wherein a first of the pair of FIFOs (an empty buffer FIFO) is configured to hold pointers to empty portions of the buffer while the second of the pair of FIFOs (a message FIFO) is configured to hold pointers to portions of the buffer having data therein.

主权项

1. An inter-processor communication (IPC) apparatus comprising:
a first processor and a second processor communicatively coupled to one another and to a shared memory by an arbitrated bus; and at least one pair of hardware queues coupled to each of the processors, each pair of hardware queues comprising a first queue associated with empty buffers of that processor and a second queue associated with buffers containing messages for that processor; wherein the first processor is configured to:
pop a first pointer from the first queue of the second processor, the first pointer associated with an empty buffer of the second processor;place a message to the second processor from the first processor in the empty buffer associated with the first pointer; andpush the first pointer to the second queue of the second processor.