VCCMIN FOR A DUAL PORT SYNCHRONOUS RANDOM ACCESS MEMORY (DPSRAM) CELL UTILIZED AS A SINGLE PORT SYNCHRONOUS RANDOM ACCESS MEMORY (SPSRAM) CELL

摘要

One or more techniques for improving Vccmin for a dual port synchronous random access memory (DPSRAM) cell utilized as a single port synchronous random access memory (SPSRAM) cell are provided herein. In some embodiments, a second word line signal is sent to a second word line of the DPSRAM cell. For example, the second word line signal is sent in response to a logical low at a first bit line or a logical low at a second bit line. In this way, Vccmin is improved for the DPSRAM cell.