PARALLEL-SERIAL CONVERSION CIRCUIT, INTERFACE CIRCUIT AND CONTROL DEVICE

摘要

PROBLEM TO BE SOLVED: To convert parallel data to serial data and easily adjust an output timing of the serial data.SOLUTION: A control code generation circuit 400 generates control signals CS0, CI0 on the basis of phase information PI0. A timing adjustment circuit 410 controls a delay time of each bit data of data IDQ0[0:3] in the unit of half (T/2) of a period of a clock signal CK1 on the basis of the control signal CS0, and delays each bit data of the data IDQ0[0:3] to output delayed data DDQ0[0:3]. A conversion circuit 420 generates a plurality of clock signals phase-adjusted relative to the clock signal CK1 on the basis of the control signal CI0. The conversion circuit 420 then converts the four-bit delayed data DDQ0[0:3] output from the timing adjustment circuit 410 to one-bit data SD0 on the basis of the plurality of clock signals.