发明名称 |
SILICON ALIGNMENT PINS: AN EASY WAY TO REALIZE A WAFER-TO-WAFER ALIGNMENT |
摘要 |
A silicon alignment pin is used to align successive layers of components made in semiconductor chips and/or metallic components to make easier the assembly of devices having a layered structure. The pin is made as a compressible structure which can be squeezed to reduce its outer diameter, have one end fit into a corresponding alignment pocket or cavity defined in a layer of material to be assembled into a layered structure, and then allowed to expand to produce an interference fit with the cavity. The other end can then be inserted into a corresponding cavity defined in a surface of a second layer of material that mates with the first layer. The two layers are in registry when the pin is mated to both. Multiple layers can be assembled to create a multilayer structure. Examples of such devices are presented. |
申请公布号 |
US2014147192(A1) |
申请公布日期 |
2014.05.29 |
申请号 |
US201313871830 |
申请日期 |
2013.04.26 |
申请人 |
JUNG-KUBIAK CECILE;RECK THEODORE;THOMAS BERTRAND;LIN ROBERT H.;PERALTA ALEJANDRO;GILL JOHN J.;LEE CHOONSUP;SILES JOSE V.;TODA RISAKU;CHATTOPADHYAY GOUTAM;COOPER KEN B.;MEHDI IMRAN;CALIFORNIA INSTITUTE OF TECHNOLOGY |
发明人 |
JUNG-KUBIAK CECILE;RECK THEODORE;THOMAS BERTRAND;LIN ROBERT H.;PERALTA ALEJANDRO;GILL JOHN J.;LEE CHOONSUP;SILES JOSE V.;TODA RISAKU;CHATTOPADHYAY GOUTAM;COOPER KEN B.;MEHDI IMRAN |
分类号 |
F16B5/00 |
主分类号 |
F16B5/00 |
代理机构 |
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代理人 |
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地址 |
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