Multi-Processor, Multi-Domain, Multi-Protocol Cache Coherent Speculation Aware Shared Memory Controller and Interconnect

摘要

This invention combines a multicore shared memory controller and an asynchronous protocol converting bridge to create a very efficient heterogeneous multi-processor system. After traversing the protocol converting bridge the commands travel through the regular processor port. This allows the interconnect to remain unchanged while having any combination of different processors connected. This invention tightly integrates all of the processors into the same memory controller/interconnect.