| 摘要 |
The present invention applies to the field of integrated circuits (ICs), and provides an IC having a scan chain and a testing method for a chip. The IC comprises a first interface group, a second interface group and a scan data selector. The first interface group and the second interface group each comprise at least two input/output (I/O) interfaces which can be packaged as external pins of the IC. The I/O interfaces of the first interface group are connected to input terminals of the scan data selector in one-to-one correspondence, and an output terminal of the scan data selector is connected to a scan data input terminal of the scan chain. A scan data output terminal of the scan chain is connected to the I/O interfaces of the second interface group. Embodiments of the present invention can considerably increase the number of scan chains and reduce the number of registers in a single scan chain, thereby considerably reducing the testing cost for the chip and increasing the testing efficiency for the chip. |
