| 摘要 |
<p>A flip-flop 340 has a high logic level permanently connected to its D input and a power-on signal 307 coupled to the direct reset input RN so that when the signal 307 goes low, even briefly, the output 308 immediately follows and remains low until the clock edge after the return of the signal 307 to a high state. The optional second flip-flop 342 ensures that any low transient, of even very short duration, in signal 307 causes signal 309 to be low for a minimum of one clock cycle. The optional further flip-flops 344 and 348 provide metastability protection. The low state of the output 313 indicates that signals from a monitored circuit, such as a non-volatile memory subject to short voltage dips, may be unreliable. The multiplexer 323 allows scan testing of the circuit by providing a controllable hard reset.</p> |
