发明名称 Multi-level vertical plug formation with stop layers of increasing thicknesses
摘要 A method is provided for use with an IC device including a stack including a plurality of conductive layers interleaved with a plurality of dielectric layers, for forming interlayer connectors extending from a connector surface to respective conductive layers. The method forms landing areas on the plurality of conductive layers in the stack. The landing areas are without overlying conductive layers in the stack. The method forms etch stop layers over corresponding landing areas. The etch stop layers have thicknesses that correlate with depths of the corresponding landing areas. The method fills over the landing areas and the etch stop layers with a dielectric fill material. Using a patterned etching process, the method forms a plurality of vias extending through the dielectric fill material and the etch stop layers to the landing areas in the plurality of conductive layers.
申请公布号 US8736069(B2) 申请公布日期 2014.05.27
申请号 US201213593328 申请日期 2012.08.23
申请人 CHIU CHIAJUNG;LEE GUANRU;MACRONIX INTERNATIONAL CO., LTD. 发明人 CHIU CHIAJUNG;LEE GUANRU
分类号 H01L23/498;H01L21/768 主分类号 H01L23/498
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