发明名称 Flash memory controller and system including data pipelines incorporating multiple buffers
摘要 A storage controller connected to a flash memory storage module, the controller and module including multiple sets of buffers. The buffers are part of one or more pipelines through which data is moved between the storage module and one or more hosts.
申请公布号 US8738841(B2) 申请公布日期 2014.05.27
申请号 US20080082220 申请日期 2008.04.08
申请人 OLBRICH AARON K.;PRINS DOUGLAS A.;SANDISK ENTERPRISE IP LLC. 发明人 OLBRICH AARON K.;PRINS DOUGLAS A.
分类号 G06F12/02 主分类号 G06F12/02
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