发明名称 |
Integrated circuits and methods for fabricating integrated circuits using double patterning processes |
摘要 |
Integrated circuits and methods for fabricating integrated circuits are provided. One method includes creating a master pattern layout including first and second adjacent cells. The first adjacent cell has a first border pin with a first routing line. The second adjacent cell has a second border pin with a second routing line. The first and second routing lines overlap to define an edge-edge stitch to couple the first and second border pins. The master pattern layout is decomposed into sub-patterns. |
申请公布号 |
US8735050(B2) |
申请公布日期 |
2014.05.27 |
申请号 |
US201213567233 |
申请日期 |
2012.08.06 |
申请人 |
YUAN LEI;YOSHIDA HIDEKAZU;KYE JONGWOOK;XIANG QI;RASHED MAHBUB;GLOBALFOUNDRIES, INC. |
发明人 |
YUAN LEI;YOSHIDA HIDEKAZU;KYE JONGWOOK;XIANG QI;RASHED MAHBUB |
分类号 |
G03F1/00;G06F17/50 |
主分类号 |
G03F1/00 |
代理机构 |
|
代理人 |
|
主权项 |
|
地址 |
|