发明名称 Layout decomposition method and method for manufacturing semiconductor device applying the same
摘要 A layout decomposition method and a method for manufacturing a semiconductor device applying the same are provided. According to the layout decomposition method, a design layout is received by the logic processer of a computing system. A design rule for layout decomposition is then identified by the logic processer, including identifying the loose areas (areas with loosely distributed features) and dense areas (areas with densely distributed features) on a substrate, and identifying first areas with odd-numbered features and second areas with even-numbered features on the substrate. Next, a first mask with a first pattern and a second mask with a second pattern are generated corresponding to results of design rule identification by the computing system.
申请公布号 US8739083(B1) 申请公布日期 2014.05.27
申请号 US201213676185 申请日期 2012.11.14
申请人 UNITED MICROELECTRONICS CORP. 发明人 TUNG YU-CHENG
分类号 G06F17/50 主分类号 G06F17/50
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