发明名称 Processors and Systems with Divided-Down Phase Change Memory Read Voltages
摘要 Methods and systems for fast, low power PCM memory using a bitline precharge scheme in which unselected bitlines are driven to predetermined voltages and a selected bitline is set to ground, such that when selected and unselected bitlines are shorted together, the selected bitline is charged to a PCM sense voltage. Inventive methods and systems do not require a precharge voltage regulator to drive selected bitlines to a sense voltage.
申请公布号 US2014140128(A1) 申请公布日期 2014.05.22
申请号 US201313869752 申请日期 2013.04.24
申请人 BEING ADVANCED MEMORY CORPORATOIN;BEING ADVANCED MEMORY CORPORATOIN 发明人 JURASEK RYAN
分类号 G11C13/00 主分类号 G11C13/00
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