发明名称 |
Embedded JFETs for High Voltage Applications |
摘要 |
A device includes a buried well region and a first HVW region of the first conductivity, and an insulation region over the first HVW region. A drain region of the first conductivity type is disposed on a first side of the insulation region and in a top surface region of the first HVW region. A first well region and a second well region of a second conductivity type opposite the first conductivity type are on the second side of the insulation region. A second HVW region of the first conductivity type is disposed between the first and the second well regions, wherein the second HVW region is connected to the buried well region. A source region of the first conductivity type is in a top surface region of the second HVW region, wherein the source region, the drain region, and the buried well region form a JFET. |
申请公布号 |
US2014139282(A1) |
申请公布日期 |
2014.05.22 |
申请号 |
US201414166475 |
申请日期 |
2014.01.28 |
申请人 |
TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD. |
发明人 |
YEH JEN-HAO;CHENG CHIH-CHANG;SU RU-YI;HUO KER HSIAO;CHEN PO-CHIH;YANG FU-CHIH;TSAI CHUN-LIN |
分类号 |
H03K17/22;H01L29/66;H01L29/808 |
主分类号 |
H03K17/22 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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