发明名称 |
INTEGRATED CIRCUITS AND METHODS FOR FABRICATING INTEGRATED CIRCUITS WITH REDUCED PARASITIC CAPACITANCE |
摘要 |
Integrated circuits and methods for fabricating integrated circuits are provided. In an embodiment, a method for fabricating an integrated circuit includes forming a sacrificial gate structure over a semiconductor substrate. A spacer is formed around the sacrificial gate structure and a dielectric material is deposited over the spacer and semiconductor substrate. The method includes selectively etching the spacer to form a trench between the sacrificial gate structure and the dielectric material. The trench is bounded by a trench surface upon which a replacement spacer material is deposited. The method merges an upper region of the replacement spacer material to enclose a void within the replacement spacer material. |
申请公布号 |
US2014138779(A1) |
申请公布日期 |
2014.05.22 |
申请号 |
US201213682331 |
申请日期 |
2012.11.20 |
申请人 |
GLOBALFOUNDRIES, INC. |
发明人 |
XIE RUILONG;CAI XIUYU;ZHANG XUNYUAN |
分类号 |
H01L29/66;H01L29/40;H01L29/78 |
主分类号 |
H01L29/66 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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