| 摘要 |
Systems and methods are disclosed for reducing or eliminating hot carrier injection stress in circuits. In one embodiment, the present invention relates to an integrated circuit comprising an IO PAD (256), an output circuit (215) coupled to at least the IO PAD (256) and a stress circuit (217). The stress circuit (217) is coupled to at least the output circuit (215) and is adapted to limit a high voltage across the output circuit (215) when the output circuit (215) is enabled, thereby reducing stress on the output circuit (215). In one embodiment, the stress circuit (217) comprises at least one transistor device (220,222), e.g. a p-channel device or two stacked p-channel devices, for example and the output circuit comprises a transistor device (224,226) e.g. an n-channel device or two stacked n-channel devices. |
