发明名称 |
Scheduling in a multicore processor |
摘要 |
A method and computer-usable medium including instructions for performing a method for scheduling executable transactions within a multicore processor comprising a plurality of processor elements. The method includes listing, using at least one distribution queue, a portion of the executable transactions in order of eligibility for execution. A plurality of executable transaction schedulers are provided, wherein each executable transaction scheduler includes a scheduling process for determining a most eligible executable transaction for execution from at least one candidate executable transaction ready for execution. The executable transaction schedulers are linked together to provide a multilevel scheduler. The most eligible executable transaction is output from the multilevel scheduler to the at least one distribution queue. |
申请公布号 |
US8732439(B2) |
申请公布日期 |
2014.05.20 |
申请号 |
US20060540146 |
申请日期 |
2006.09.29 |
申请人 |
LIPPETT MARK D.;SYNOPSYS, INC.;FUJITSU SEMICONDUCTOR LIMITED |
发明人 |
LIPPETT MARK D. |
分类号 |
G06F9/30;G06F1/32;G06F9/40;G06F15/00 |
主分类号 |
G06F9/30 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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