发明名称 |
Logical address translation |
摘要 |
The present disclosure includes methods for logical address translation, methods for operating memory systems, and memory systems. One such method includes receiving a command associated with a LA, wherein the LA is in a particular range of LAs and translating the LA to a physical location in memory using an offset corresponding to a number of physical locations skipped when writing data associated with a range of LAs other than the particular range. |
申请公布号 |
US8732431(B2) |
申请公布日期 |
2014.05.20 |
申请号 |
US201113041402 |
申请日期 |
2011.03.06 |
申请人 |
CULLEY MARTIN L.;MANNING TROY A.;LARSEN TROY D.;MICRON TECHNOLOGY, INC. |
发明人 |
CULLEY MARTIN L.;MANNING TROY A.;LARSEN TROY D. |
分类号 |
G06F12/00;G06F3/06;G06F12/02;G06F12/04;G06F12/10;G06F12/14 |
主分类号 |
G06F12/00 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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