| 摘要 |
A semiconductor device comprising a first inverter circuit including a first PMOS transistor and a first NMOS transistor, a drain electrode of the first PMOS transistor coupled to a drain electrode of the first NMOS transistor, and a second inverter circuit including a second PMOS transistor and a second NMOS transistor, a drain electrode of the second PMOS transistor coupled to a drain electrode of the second NMOS transistor. A first output voltage pad coupled to gate electrodes of the first and second PMOS and NMOS transistors, and between the drain electrode of the first PMOS transistor and the drain electrode of the NMOS transistor to self-bias the first inverter circuit. A second output voltage pad coupled between the drain electrode of the second PMOS transistor and the drain electrode of the second NMOS transistor. |
