Circuits and methods for placing programmable impedance memory elements in high impedance states

摘要

A memory device can include a load circuit coupled in series with at least one memory element between two nodes and configured to enable a programming current to flow through the memory element to lower its impedance, and configured to enable an erase current to flow through the element in a direction opposite to the program current, the erase current varying in response to an erase voltage applied across the two nodes as the memory element impedance increases.