Verifying proper representation of semiconductor device fingers

摘要

A system for verifying that device fingers of a semiconductor circuit have been properly represented by a corresponding layout diagram. The system determines a plurality of sub-circuits, from within a netlist of a schematic diagram, to be verified. Each sub-circuit of the plurality of sub-circuits includes a multi-finger device. The system also determines a first number of fingers included in the plurality of sub-circuits as represented by the schematic diagram. The system also determines a second number of fingers included in the plurality of sub-circuits as represented by the corresponding layout diagram. The system compares the first number of fingers against the second number of fingers. The system reports an error if the first number of fingers does not correspond to the second number of fingers.