发明名称 System and methods for handling verification errors
摘要 Systems, apparatus and methods for handling verification violations are disclosed. In one aspect, a method stores a list of fix information in addition to geometric shapes for each layer during verification, such as design rule checking For each primitive operation step performed during verification, two tasks are performed. First, if the primitive operation is a dimensional checking operation (i.e., width, spacing or enclosure), then for each violation, the first task creates fix information containing violation edge pairs and adds the created fix information to the fix information list on the output layer. Second, for all operations and after the output shapes on the output layer are generated, a second task passes the fix information on input layers which overlap any output shape of the output layer to the output layer's fix information list. Finally, fix guides for the final violation results are generated and drawn based on the final fix information list.
申请公布号 US8732631(B2) 申请公布日期 2014.05.20
申请号 US201313833167 申请日期 2013.03.15
申请人 SYNOPSYS, INC. 发明人 FANG MIN-YI;NIAN KAI-JYUN;WU ZHEN-MIN;CHANG SHUN-CHIN;SU YU-CHI
分类号 G06F17/50 主分类号 G06F17/50
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