发明名称 Error floor reduction in iteratively decoded FEC codes
摘要 A method which makes use of the syndrome information at each iteration, combined with the bit reliability information available at a FEC decoder, to extract the minimum estimated bit error configuration, i.e. the block which is closest to the transmitted codeword during the decoding process, and to select such block if the result at the final decoding iteration has a higher number of estimated bit errors.
申请公布号 US8732564(B2) 申请公布日期 2014.05.20
申请号 US201013574660 申请日期 2010.01.27
申请人 CHINNICI STEFANO;DECANIS CARMELO;TELEFONAKTIEBOLAGET L M ERICSSON (PUBL) 发明人 CHINNICI STEFANO;DECANIS CARMELO
分类号 H03M13/00 主分类号 H03M13/00
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