发明名称 System on chip fault detection
摘要 The invention relates to a method for fault identification in a System-on-Chip (SoC) consisting of a number of IP cores, wherein each IP core is a fault containment unit, and where the IP cores communicate with one another by means of messages via a Network-on-Chip, and wherein an excellent IP core provides a TRM (Trusted Resource Monitor), wherein a faulty control message which is sent from one non-privileged IP core to another non-privileged IP core is identified and projected by an (independent) fault container unit, as a result of which this faulty control message cannot cause any failure of the message receiver.
申请公布号 US8732522(B2) 申请公布日期 2014.05.20
申请号 US201013383011 申请日期 2010.07.07
申请人 POLEDNA STEFAN;FTS COMPUTERTECHNIK GMBH 发明人 POLEDNA STEFAN
分类号 G06F11/00 主分类号 G06F11/00
代理机构 代理人
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