| 摘要 |
PROBLEM TO BE SOLVED: To enable the signal type of a signal outputted from each channel to be easily changed, and to restrain a noise component from getting mixed in a data signal.SOLUTION: A clock parallel type serializer circuit 1 comprises: a PLL unit 20 for generating a multiply-by-1 first clock signal 104 on the basis of an inputted reference clock 103 and a second clock signal 105 derived by multiplying the reference clock 103 by a prescribed factor; a plurality of data/clock shared channel units 10 for generating, on the basis of an inputted data/clock selection signal 102, either 1-bit serial data converted from inputted multiple-bit parallel data or a clock signal for synchronizing a receiving circuit side and outputting the generated data or signal as a signal 107; and a load pulse generation unit 30 for generating, on the basis of the second clock signal 105, a load pulse signal 106 for determining output timing for a signal outputted from the plurality of data/clock shared channel units 10. |
