| 摘要 |
The present invention relates to a serial link synchronizing method in a SerDes network capable of correctly arranging data irrespective of a data width difference and a clock frequency difference between a transmitting side and a receiving side. The serial link synchronizing method in the SerDes network according to the present invention comprises the following steps: (a) making an FPGA, having a pair of SerDes transceivers functioning as a receiving transceiver and a transmitting transceiver, check whether a link-on signal is in a state capable of transmitting data while continuously receiving the data at the receiving transceiver; (b) making the FPGA waste the currently received data in the case that the link-on signal is not in a state capable of transmitting the data as a check result of the (a) step and making the FPGA check whether the currently received data is start data of a packet in the case that the link-on signal is in a state capable of transmitting the data; and making the FPGA waste the currently received data in the case that the currently received data is not the start data of the packet as a result of the (b) step and transmit the currently received data via the transmission transceiver in the case that the currently received data is the start data of the packet. In the forementioned configuration, determining whether the currently received data is the start data of the packet is performed by using the K-character of a 16b/20b encoder and decoder used in the SerDer transceiver. |
