发明名称 CORRECTION METHOD OF LAYOUT PATTERN
摘要 PROBLEM TO BE SOLVED: To shorten time taken for OPC processing of a photomask pattern.SOLUTION: A correction method of a layout pattern includes: a process in which a function block region corresponding to a function block is detected from a layout pattern of an integrated circuit; a process in which a size to divide the function block region is determined based on a pattern density of the function block region; a process in which the function block region is divided to the determined size to generate a unit area; and a process in which the unit area is subjected to OPC processing by a computer.
申请公布号 JP2014092655(A) 申请公布日期 2014.05.19
申请号 JP20120242617 申请日期 2012.11.02
申请人 FUJITSU SEMICONDUCTOR LTD 发明人 YOSHIOKA HIROTAKA;MINEMURA MASAHIKO;SUGAWA KAZUYA
分类号 G03F1/36;H01L21/027;H01L21/82 主分类号 G03F1/36
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