| 摘要 |
PROBLEM TO BE SOLVED: To transfer data properly at a high speed.SOLUTION: In an image forming apparatus 1, a controller ASIC 21 generates a false line synchronization signal of the same period as a line synchronization signal to be output from a plotter 33 to an engine ASIC 31, and transfers image data of a memory 25 in synchronization with the false line synchronization signal. The engine ASIC 31 detects the amount of receiving time lag between the image data and the line synchronization signal, and outputs a data receiving timing error signal to the controller ASIC 21 when a data receiving timing error determination value is exceeded. On receipt of the error signal, the controller ASIC 21 corrects generation timing of the false line synchronization signal, to perform data transfer at the same timing as transfer in synchronization with the line synchronization signal. |
