| 摘要 |
The use of eye pattern circuitry associated with a serial receiver embedded in an integrated circuit (e.g. in an FPGA) relies on the signal quality and signal frequency being sufficient for the serial receiver to lock onto the signal: if this is not possible then it is not possible to obtain an eye pattern. Our novel invention enables the use of this embedded circuitry where the signal quality and signal frequency are not sufficient by splitting the incoming signal, then using the clock recovered with further processing from one of the split signals together with the built-in eye pattern circuitry to obtain a realistic eye pattern for the unprocessed signal, regardless of the quality of that unprocessed signal. The technique uses the free-running or‘slave’mode of these serial receivers in which the receiver does not lock to the incoming data. To date, this mode has been used for oversampling but not for sampling at the actual data rate with a recovered clock in order obtain eye pattern samples. |
