| 摘要 |
Disclosed is a polybinary-signal generator in which correlative coding is applied to a plurality of fractional-bit-rate signals instead of being applied to a corresponding multiplexed full-bit-rate signal. The resulting coded fractional-bit-rate signals are variously delayed with respect to one another and then summed to generate a polybinary output signal. One beneficial feature of this architecture is that most circuit components of the polybinary-signal generator operate at the fractional bit rate, which helps to alleviate at least some of the technical difficulties associated with the design of radio-frequency circuits intended for relatively high bit rates. Another beneficial feature of this architecture is that the polybinary-signal generator also serves as a signal multiplexer. |
