发明名称 CMOS LOGIC CIRCUIT USING PASSIVE INTERNAL BODY TIE BIAS
摘要 This disclosure is directed to devices, integrated circuits, systems, and methods for implementing an internal body tie bias circuit in a CMOS logic circuit. In one example, a CMOS logic circuit is formed in an integrated circuit. The CMOS logic circuit includes a PMOS transistor, an NMOS transistor; and a body tie bias circuit formed in the integrated circuit. The body tie bias circuit is coupled between a body tie connection terminal of the PMOS transistor and a body tie connection terminal of the NMOS transistor.
申请公布号 US2014132306(A1) 申请公布日期 2014.05.15
申请号 US201213675828 申请日期 2012.11.13
申请人 HONEYWELL INTERNATIONAL INC. 发明人 FECHNER PAUL S.;ROPER WESTON;SEEFELDT JAMES D.
分类号 H03K19/094 主分类号 H03K19/094
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