METAL GATE MOS TRANSISTOR WITH REDUCED GATE-TO-SOURCE AND GATE-TO-DRAIN OVERLAP CAPACITANCE

摘要

The gate-to-source and gate-to-drain overlap capacitance of a MOS transistor (200) with a metal gate (230) and a high-k gate dielectric (226) are reduced by forming the high-k gate dielectric (226) along the inside of a sidewall structure (236) which has been formed to lie further away from the source (220) and the drain (222).