发明名称 |
RESISTIVE RANDOM ACCESS MEMORY EQUALIZATION AND SENSING |
摘要 |
Providing for a two-terminal memory architecture that can mitigate sneak path current in conjunction with memory operations is described herein. By way of example, a voltage mimicking mechanism can be employed to dynamically drive un-selected bitlines of the memory architecture at a voltage observed by a selected bitline. According to these aspects, changes observed by the selected bitline can be applied to the un-selected bitlines as well. This can help reduce or avoid voltage differences between the selected bitline and the un-selected bitlines, thereby reducing or avoiding sneak path currents between respective bitlines of the memory architecture. Additionally, an input/output based configuration is provided to facilitate reduced sneak path current according to additional aspects of the subject disclosure. |
申请公布号 |
US2014133211(A1) |
申请公布日期 |
2014.05.15 |
申请号 |
US201213676943 |
申请日期 |
2012.11.14 |
申请人 |
CROSSBAR, INC.;CROSSBAR, INC. |
发明人 |
NAZARIAN HAGOP;NGUYEN SANG |
分类号 |
G11C7/12;G11C5/12;G11C11/02;G11C11/34 |
主分类号 |
G11C7/12 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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