CLOCK SIGNAL INITIALIZATION CIRCUIT AND METHOD

摘要

PROBLEM TO BE SOLVED: To provide a clock signal initialization circuit that keeps the operating frequency of a semiconductor integrated circuit within a maximum permissible frequency based on the power consumption of the semiconductor integrated circuit even in a startup transient state of a PLL circuit.SOLUTION: The clock signal initialization circuit for a semiconductor integrated circuit that operates in synchronism with a clock signal generated by the PLL circuit (1) includes control means (5, 2, 3) for controlling to derive a clock signal of a frequency within a maximum permissible frequency based on the power consumption of the semiconductor integrated circuit as a supply clock signal to the semiconductor integrated circuit at least until the PLL circuit is in a locked state after power input.