| 摘要 |
<p>A transmitting bus interface (110) inserts clock mismatch compensation symbols into a transmitted data stream (128) so as to allow the receiving bus interface (122) to compensate for clock frequency mismatch between transmit-side and receive-side clocks (134, 136). The transmitting bus interface adjusts the rate of insertion of these symbols based on a determination of the clock frequency mismatch. The transmitting bus interface can incrementally adjust the insertion rate to change substantially proportionally with changes in the clock frequency mismatch. Alternatively, the transmitting bus interface can set the insertion rate to one of two levels. By adapting the insertion rate to the current measured clock frequency mismatch, the bandwidth penalty incurred by transmitting clock mismatch compensation symbols in excess of that necessary to permit receiver clock tolerance compensation can be reduced, thereby permitting more transmit bandwidth to be used for transmitting data.</p> |
