发明名称 SEMICONDUCTOR MEMORY AND SEMICONDUCTOR MEMORY MANUFACTURING METHOD
摘要 PROBLEM TO BE SOLVED: To improve the reliability of a semiconductor memory by applying a voltage stress between bit lines adjacent to each other in a sense amplifier region.SOLUTION: The semiconductor memory comprises: a first cell array including a plurality of first bit lines; a second cell array including a plurality of second bit lines; a plurality of first sense amplifiers and a plurality of second sense amplifiers arranged in parallel between the first and second cell arrays; a plurality of first precharge circuits each connecting the first and second bit lines connected to the first sense amplifier with a first precharge voltage line; a plurality of second precharge circuits each connecting the first and second bit lines connected to the second sense amplifier with a second precharge voltage line; and a voltage supply section that, in a test mode, supplies one of a high-level voltage or a low-level voltage to the first precharge voltage line, and supplies the other of the high-level voltage or the low-level voltage to the second precharge voltage line.
申请公布号 JP2014089784(A) 申请公布日期 2014.05.15
申请号 JP20120240052 申请日期 2012.10.31
申请人 FUJITSU SEMICONDUCTOR LTD 发明人 NAKAMURA TOSHIKAZU
分类号 G11C29/06;G11C11/401;G11C11/4094 主分类号 G11C29/06
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