| 摘要 |
A power semiconductor device having an n + buffer layer (56) provided on a p + collector layer (55); an n - layer (57) provided on the n + buffer layer (56); a p base region (66) provided selectively in the top side of the n - layer (57); an n + emitter region (6, 9) provided selectively in the top side of the p base region (66); one or two trench gate electrodes (3, 4, 8) each composed of a trench (3a, 4a, 8a) that extends from a top side of the p base region (66), with the trench bottom portion reaching into the n - layer (57), a gate insulation film (3b, 4b, 8b) lining the trench (3a, 4a, 8a), and a gate electrode (3c, 4c, 8c) filling the trench; an emitter electrode (51) that is provided on the p base region (66) and is electrically connected with the n + emitter region (6, 9); and a collector electrode (63) provided on the bottom side of the p + collector layer (55). The n + emitter region (6, 9) is provided contiguously bordering on only one side of each of the one or two trench gate electrodes (3, 4, 8). Therefore the cross-sectional area of the gate electrode (3, 4, 8) per n + emitter region (6, 9) is increased, whereby the gate electrode resistance is lowered and imbalance between cells at turn-off is reduced, so that increased current capacity and higher reliability can be achieved even when spaces for the emitter electrode (51) in a gate wiring (53) become wide. |
