| 摘要 |
A memory device that includes an input interface that receives instructions and input data on a first plurality of serial links. The instructions and input data are deserialized on the memory device, and are provided to a memory controller. The memory controller initiates accesses to a memory core in response to the received instructions. The memory core includes a plurality of memory partitions, which are accessed in a cyclic and overlapping manner. This allows each memory partition to operate at a slower frequency than the serial links, while properly servicing the received instructions. Accesses to the memory device are performed in a synchronous manner, wherein each access exhibits a known fixed latency. |
