发明名称 PHASE SHIFTING IN DLL/PLL
摘要 <p>The disclosure relates to phase shifting in Delay Locked Loops (DLLs) and Phase-Locked Loops (PLLs). A charge pump in the DLL or PLL includes a capacitor connected in parallel to an output node. A primary current switching circuit charges the capacitor with a source current and discharges the capacitor with a sink current. A supplemental source circuit sources a positive phase shift producing current which has a range of magnitudes. A magnitude of the positive phase shift producing current is determined by at least one source selection signal. A supplemental sink circuit for sources a negative phase shift producing current which has a range of magnitudes. A magnitude of the negative phase shift producing current is determined by at least one sink selection signal.</p>
申请公布号 KR101394869(B1) 申请公布日期 2014.05.13
申请号 KR20137031964 申请日期 2008.01.29
申请人 发明人
分类号 H03L7/089;H03K5/134;H03L7/099 主分类号 H03L7/089
代理机构 代理人
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