发明名称 |
Register file system and method for pipelined processing |
摘要 |
The present disclosure includes a multi-threaded processor that includes a first register file associated with a first thread and a second register file associated with a second thread. At least one hardware resource is shared by the first and second register files. In addition, the first thread may have a pipeline access position that is non-sequential to the second thread. A method of accessing a plurality of register files is also disclosed. The method includes reading data from a first register file while concurrently reading data from a second register file. The first register file is associated with a first instruction stream and the second register file is associated with a second instruction stream. The first instruction stream is sequential to the second instruction stream in an execution pipeline of a processor, and the first register file is in a non-adjacent location with respect to the second register file. |
申请公布号 |
US8725991(B2) |
申请公布日期 |
2014.05.13 |
申请号 |
US20070853866 |
申请日期 |
2007.09.12 |
申请人 |
WANG LIN;KAMAL MASUD;BASSETT PAUL;VENKUMAHANTI SURESH;SHEN JIAN;QUALCOMM INCORPORATED |
发明人 |
WANG LIN;KAMAL MASUD;BASSETT PAUL;VENKUMAHANTI SURESH;SHEN JIAN |
分类号 |
G06F9/30;G06F9/40;G06F15/00 |
主分类号 |
G06F9/30 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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