发明名称 Information processing apparatus and memory control apparatus
摘要 A memory control apparatus, in a case of receiving from a processor, under a condition where the number of cache memories retaining a copy of data stored in a main storage device is one, a notification to the effect that data retained in the cache memory is purged, updates directory information on a directory cache without accessing the main storage device when the data is not modified by the processor, and the directory information on the directory cache and directory information on the main storage device is determined to be different and the directory information on the main storage device is determined to be in a state indicating that the copy of the data is not retained by any processor in the state of coherence.
申请公布号 US8725954(B2) 申请公布日期 2014.05.13
申请号 US201113101362 申请日期 2011.05.05
申请人 MAEDA KOICHI;WADA HIROYUKI;FUJITSU LIMITED 发明人 MAEDA KOICHI;WADA HIROYUKI
分类号 G06F12/00 主分类号 G06F12/00
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